Native Tess
Tess packs INT8 or BF16 into MlaTiled without changing logical values or bit
patterns. Detess provides the inverse. The operations
share their typed requests with A65. They do not invoke the older standalone
graph interfaces or parse ConfigManager/JSON configuration.
Contract
Tess requires equal explicit input/output shapes and dtypes, rank
1–6, and a unique D/H/W/C mapping with C present. Unmapped axes are independent
outer dimensions. Empty tensors need no storage or device submission. Rank-zero
scalars, MlaCBlocked, in-place execution and other scalar dtypes are rejected.
The linear side admits scalar-aligned, conservatively nonoverlapping strides. Negative strides, broadcast on nonunit axes and overlapping views are unsupported. The required span includes holes; the caller supplies the actual accessible capacity. Detess writes logical output elements only and leaves stride gaps unchanged. See tensor storage.
Parameters and padding
ops::tess::Params::int8_channel_padding is an optional raw INT8 fill value,
required explicitly for INT8 PadTo16. It is unused for Compact and rejected
for BF16. If your next consumer requires encoded quantized-zero padding, supply
that encoded value. Tess does not infer it or perform quantization.
BF16 channel padding contains positive-zero bits. Alignment-only bytes at the end of each tile are zero for both dtypes. Required output padding is written on each Tess execution, including when a reused buffer contains dirty bytes. Detess ignores input channel and alignment padding. Storage beyond the current required span is not part of either operation's output contract.
Bit-preserving data movement
Tiles follow the shared C/D/H/W traversal, with D/H/W/C pixels within each tile. INT8 moves one byte per channel. BF16 splits each pixel into its low-channel-byte plane followed by its high-channel-byte plane; Detess joins those bytes again. There is no float conversion, rounding, saturation or dependence on FP control state. NaN payloads, signaling bits, subnormals and signed zero are unchanged.
MlaCBlocked is not an alternative label for this format. In particular, equal
storage capacity does not establish equivalent pixel/channel ordering.
Calling and lifecycle
Use ops::tess::Request or ops::detess::Request, explicit tensor specifications,
and the normal shared check_inference() boundary. The A65 Tess
and A65 Detess pages contain public-call snippets.
EV codecs add device representability checks and produce versioned relocatable
packets; C++ Plan objects are not serialized as device controls.
Runtime owns DMA-BUF mapping, coherency, submission, completion and recovery. Owners and prepared metadata remain alive until confirmed retirement, not just until submission returns. Synchronous use waits for the same submitted job. Missing native firmware capability is an error, not a request for a hidden CPU fallback. Native graph registration requires explicit matching firmware composition.
Execution and ownership
Direction and dtype select native layout-specific implementations. The native
entry validates the packet and chooses an INT8 or BF16 worker once per job.
Each worker compiles the same per-direction implementation body with a constant
one-byte or two-byte scalar width. This removes runtime dtype branches from
address calculation, staging and packing without duplicating the algorithm or
changing the public request, packet layout or worker-count contract. The native
entry keeps a separate cached kernel handle for each dtype; it does not select
by tensor name or benchmark shape. Tess owns
physical output regions, including padding. Detess owns destination regions;
contiguous output and strided output need different write-ownership proofs.
For BF16 Tess pixel bands, a partial PadTo16 channel plane is cleared with
one complete 16-byte store per byte plane before valid channels are written.
Only the final owned block of each plane is cleared; valid values overwrite
its prefix, preserving every BF16 bit pattern. Compact and fully occupied
planes skip clearing. A small band-level helper keeps the vector-zero value
out of the DMA/addressing loop's live registers without adding scratch storage
or a per-pixel call. Fragmented panel boundaries retain exact-width handling.
Input/output staging is bounded and independent of total tensor size. Tess uses two output slots to overlap output transfer with subsequent work. Input gathers retire before consumption; input/compute overlap is not claimed. Oversized pitches use at most four independent row reads per wait group instead of narrowing the 16-bit DMA fields. Scratch reuse waits for prior DMA completion. Parallel work is indexed by the actual launched logical grid, not by physical CPU IDs. Transfer alignment alone is not proof of safe concurrent accesses to a shared physical write granule.
Tests and qualification
Each direction is checked against independently constructed physical bytes. Round trips and comparisons with BF16 identity modes of fused operations are supplementary: matching inverse bugs can pass a round trip. Coverage includes INT8/BF16 bit patterns, depth and outer axes, partial tiles, padding, strides, exact capacities, dirty reuse and worker-count boundaries. Host actual-source DMA fixtures exercise delayed completion; they do not emulate EV ISA or prove hardware coherency.
Host checks, private compiler builds, real-device correctness and median latency qualification are separate evidence. New-op timing without a reviewed compatible baseline is measurement-only. Legacy standalone kernels are not correctness authorities or automatically valid performance baselines. See build requirements and qualification.
C++ call
Place the includes and namespace aliases at file scope; the remaining statements
belong in a simaai::kernels::Status-returning caller function. It checks metadata and
encodes a relocatable descriptor, not EV74 computation. Runtime must map actual
buffers, bind addresses and retain inputs, outputs and any workspace until
confirmed device completion.
#include <array>
#include <simaai/kernels/ev74/tess.h>
#include <simaai/kernels/ops/tess.h>
namespace k = simaai::kernels;
namespace op = k::ops::tess;
namespace ev = k::ev74::tess;
k::MlaTiled tiled;
tiled.axes = {-1, -1, 0, 1}; // Shape [W,C], with an explicit channel axis.
tiled.tile_shape = {1, 1, 2, 3};
const std::array inputs{k::TensorSpec{{2, 3}, k::DType::BFloat16}};
const std::array outputs{k::TensorSpec{{2, 3}, k::DType::BFloat16, tiled}};
const op::Request request{inputs, outputs, op::Params{}};
auto checked = op::check_inference(request);
if (const auto *error = std::get_if<k::Error>(&checked)) return *error;
const auto &plan = std::get<op::Plan>(checked);
auto encoded = ev::encode_relocatable(plan);
if (const auto *error = std::get_if<k::Error>(&encoded)) return *error;
// Encoding leaves device addresses unbound; no device work has run.
return {};
See the host contract tests (EV74/tess/tests/correctness.cpp) and
device fixture (EV74/tess/tests/runtime_e2e.cpp) for binding and execution coverage.
Shared exact C2 Pad16 publication
Packed two-channel INT8 rows use the same byte-only publisher as QuantTess. Eight pixels fill a sixteen-byte input vector; each output pixel owns its entire Pad16 block and receives the current invocation's padding byte. Incomplete prefixes retain exact-width source reads and output stores. BF16 planes, compressed tiles and other channel counts retain their existing numerical and storage routes.