Kernel support matrix
A65 calls use explicit input/output specifications and borrowed CPU-accessible
buffers. EV74-only contracts and device ownership are listed separately below. check_inference() rejects unsupported combinations before dispatch.
A shape has up to six logical dimensions, not an implicitly padded rank of six.
| Operation | Input → output | Layout | Rank | Parameters |
|---|---|---|---|---|
| Cast | FP32 ↔ BF16 | Contiguous or admitted strides on either port | 0–6 | None |
| Dequant | INT8 → FP32/BF16 | Contiguous or independent strided views | 0–6 | Required positive scale; zero point defaults to zero |
| Quant | BF16 / FP16 / FP32 → INT8 | Contiguous or independent strided views | 0–6 | Required positive multiplier; zero point and rounding have defaults |
| CastTess | BF16 / FP16 / FP32 → BF16 | Contiguous / admitted Strided → MlaTiled | 1–6 | None |
| QuantTess | BF16 / FP16 / FP32 → INT8 | Contiguous / admitted Strided → MlaTiled | 1–6 | Quant parameters |
| DetessCast | BF16 → FP32 / BF16 | MlaTiled / MlaCBlocked → contiguous / admitted Strided | 1–6; CBlock 3–6 | None; FP16 is unsupported |
| DetessDequant | INT8 → FP32 / BF16 | MlaTiled / MlaCBlocked → contiguous / admitted Strided | 1–6; CBlock 3–6 | Dequant parameters |
| Tess | INT8 / BF16 → same dtype | Contiguous / admitted Strided → MlaTiled | 1–6 | Explicit INT8 channel fill for PadTo16 |
| Detess | INT8 / BF16 → same dtype | MlaTiled → contiguous / admitted Strided | 1–6 | None |
| Argmax | INT8 / UINT8 / BF16 / FP32 → INT32 | Dense or admitted positive strides; INT8 / UINT8 / BF16 also accept MLA layouts → contiguous | 1–6 | Axis and keepdims |
| BoxDecode | INT8 / BF16 predictions → typed detection/auxiliary outputs | Recipe-specific dense/padded or MlaCBlocked → contiguous outputs | 3–6, singleton outer axes | Family recipe, heads, image sizes, thresholds, maximum detections; quantization only for INT8 ports |
| SuperPoint | INT8 / BF16 / FP32 logits and descriptors → FP32 points/scores, typed descriptors, INT32 count | Contiguous or dense HWC Strided with pixel channel padding; INT8/BF16 also admitted MlaCBlocked / MlaTiled → contiguous | 3–6, singleton outer axes | Explicit profile, image geometry, capacity, thresholds; quantization for INT8 ports |
Lifecycle and numerical restrictions
- Cast and the transform operations preserve logical shape. Scalars have one element; empty non-scalar shapes require no storage where admitted.
- Argmax rejects an empty reduction axis, allows empty non-reduced dimensions, and can return a scalar. First equal index wins; the first NaN wins.
- BoxDecode requires positive admitted dimensions and a context per in-flight execution. It emits four common tensors, with an additional tensor for pose, segmentation or RCNN proposal levels. It is not arbitrary batched decoding.
- SuperPoint uses a separate context per active invocation and an explicitly supplied shared host task service; it has no private worker pool.
- Successful execution does not allocate. BoxDecode and SuperPoint preparation/context creation can allocate and throw; ordinary simple plans use fixed owned metadata.
- Cast, CastTess, DetessCast and Argmax use bit-defined conversions/comparisons. Quant, Dequant, QuantTess, DetessDequant and BoxDecode impose operation-specific FP-environment requirements; see their references. The kernel does not silently change the caller's floating-point mode.
- Quant's multiplier is not Dequant's scale. BoxDecode quantization is per INT8 input port; it is not a global automatic conversion.
- Eleven operations provide host scalar execution for development. BoxDecode requires AArch64/NEON. Only an A65 target run qualifies A65 latency.
MlaTiled and MlaCBlocked are different physical representations. A tiled
transform's output must not be passed as a channel-blocked input just by changing
its descriptor. Use a matching producer/consumer contract.
Shared EV74 host contracts
Cast, Dequant, Quant, CastTess,
QuantTess,
DetessCast and
DetessDequant also expose
backend-neutral ops::* requests and EV74 host codecs. CastTess admits the same
input dtypes, rank and input-stride rules as its A65 row above and produces the
same explicit MlaTiled BF16 contract. EV admission additionally checks device
representation limits. Runtime owns asynchronous submission and must verify a
matching native firmware capability. Host support does not establish device
qualification, nor does it imply all other EV families already share this API.
DetessCast shares its A65 row's exact BF16 bit semantics, axis mappings and linear-output stride admission. Native device capability and composed-firmware qualification are separate from host codec availability.
DetessDequant shares its A65 row: MlaTiled / MlaCBlocked INT8 input,
contiguous or admitted strided FP32/BF16 output,
positive finite scale and full INT32 zero point. BF16 narrowing follows the
separately rounded FP32 subtraction and multiplication, not a lower-precision
arithmetic approximation. Legacy INT16/INT32 and FP16 routes do not extend this
native contract.
Pure layout transforms
Tess and Detess preserve every INT8 byte and BF16 bit. Their shared requests admit strides on the linear side, as do the fused DetessCast and DetessDequant output contracts. Linear strides must be scalar-aligned, positive on nonunit axes and pass the nonoverlap/span checks. Output holes remain untouched. Neither pure layout operation performs floating-point arithmetic.
Tess requires an explicit int8_channel_padding for INT8 PadTo16. This is a
raw encoded fill value, not an inferred quantization zero point. BF16 channel
padding and tile-alignment bytes are zero. Detess ignores input padding and
preserves strided output gaps. MlaCBlocked remains a different, unsupported
layout for these operations. See the native EV boundary
for backend admission, DMA ownership and qualification boundaries.
EV74-only preprocessing
Native Preproc accepts positive dense or row/frame-pitched UInt8
Gray/RGB/BGR/NV12/I420/NV16 image planes with trailing H,W,C, rank 3–6. It
produces contiguous UInt8/INT8/BF16/FP16 or UInt8/INT8/BF16 MlaTiled output.
It accepts positive row/frame input pitches with packed pixels/channels, rejects
arbitrary input strides and strided output, and rejects A65 execution without CPU fallback.
The operation page defines ROI/resize/color, arithmetic order and padding.
RGB/BGR/Gray additionally support bounded ROI lists (up to 50 output slots),
source-frame selection, per-ROI destination rectangles, raw virtual-image padding
and explicit empty-list zeroing.
EV74-only features and tracking
All four operations use explicit contiguous tensors and typed requests. Images
are UInt8, rank 3–6, with trailing H,W,1; leading axes identify independent
images and are preserved. None has an A65 fallback.
| Operation | Additional inputs | Outputs | Parameters |
|---|---|---|---|
| Histogram | None | INT32 [outer...,256] | None |
| FAST | None | Separate INT32 points/scores/count, or packed INT32 [outer...,1+3*K] | Threshold, output encoding, optional grid columns/rows and minimum distance |
| FAST+BRIEF | None | Separate FAST outputs plus UInt8 [outer...,K,32], or packed features plus INT32 [outer...,K,8] | Threshold, output encoding, optional grid columns/rows and minimum distance |
| Tracker | Previous/current images, INT32 or FP32 seed points, INT32 device-resident count, optional prior status | FP32 points [outer...,K,2], INT32 status [outer...,K] | Window half-size, iteration limit, pyramid levels |
For FAST and FAST+BRIEF, omitting the grid preserves raster-first selection. See grid selection and spacing for quota and ordering rules, and named fields for generic callers.
Image limits, content-dependent count/status handling, truncation order and numerical rules are operation-specific. Read the linked contracts. Feature capacity comes from explicit output shapes; it does not trigger dynamic output allocation. Runtime must bind and retain every input, output and workspace until completion. Host/source-model checks and private compilation are available; matching-device correctness and fresh baseline-qualified latency are still required before claiming target acceptance.
EV74 SIMOR camera depth
SIMOR depth map accepts six dense, batch-one inputs: I420 Y/U/V, UINT16 disparity and FP32 calibration tensors. It produces RGB UINT8, depth UINT16 in millimetres and XYZ FP32 in metres. There is no A65 fallback. See the operation contract for geometry and alignment.