A65 kernels
The experimental 0.1.0 C++20 API exposes typed preparation and synchronous
CPU-visible execution. A65 is selected by the namespaced entrypoint, not by a
hidden hardware selector or an untyped parameter dictionary.
| Operation | Purpose |
|---|---|
| Cast | FP32/BF16 conversion |
| Dequant | INT8 to FP32/BF16 dequantization |
| Quant | BF16/FP16/FP32 to INT8 quantization |
| CastTess | Conversion and MLA packing |
| QuantTess | Quantization and MLA packing |
| DetessCast | MLA BF16 unpacking and conversion |
| DetessDequant | MLA INT8 unpacking and dequantization |
| Tess | Bit-preserving MLA packing |
| Detess | Bit-preserving MLA unpacking |
| Argmax | Logical-axis index reduction |
| BoxDecode | Explicit detection, pose, segmentation and proposal recipes |
| SuperPoint | Detector logits and coarse descriptors to native feature-point tensors |
Start with calling kernels, tensor storage, and the support matrix. Shape capacity is six dimensions; individual operations impose different rank, empty-tensor and layout restrictions.
Eleven operations have portable host routes for development. BoxDecode requires AArch64/NEON. Host results do not qualify A65 performance. See build and test for the supported execution workflows.