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Detess

Detess changes physical storage without changing logical tensor values or dtype. It is a layout operation, not a cast or a quantization operation.

Contract​

  • Direction: Explicit MlaTiled → contiguous or admitted Strided.
  • Same dtype on both ports: INT8 or BF16. FP16, FP32, UINT8 and wider integers are not admitted by this MLA-facing contract.
  • Equal explicit logical shapes with rank 1–6. Empty extents are allowed; rank-zero scalars are rejected. Six is capacity, not implicit leading ones.
  • D/H/W/C axes are explicit and unique; C is required. Omitted spatial axes have extent/tile extent one. Unmapped logical axes remain independent outer axes.
  • Compact and PadTo16 are supported. MlaCBlocked is a different physical representation and is rejected.
  • Strides are nonnegative, scalar-aligned and conservatively proven nonoverlapping. Broadcast/negative/overlapping views are rejected; zero stride requires an extent of at most one. The sorted-span proof can reject unusual injective views.

The same shared request is admitted before selecting A65 or EV74. Backend representability checks remain additional preparation checks, not new semantics.

Parameters​

Params is empty. Geometry and dtype are explicit tensor metadata. Input channel and alignment padding are ignored: Detess needs no fill value, quantization scale or zero point.

Numerical behavior​

For each logical scalar, locate its mapped input tile. Copy INT8's stored byte, or join BF16's low and high channel bytes into the original two-byte word. Write only the logical output scalar, leaving strided output gaps untouched. Ignore input channel/alignment padding without modifying it. No conversion, rounding, saturation, dequantization or floating-point arithmetic occurs.

Every BF16 bit pattern is preserved, including signaling/quiet NaN payloads, subnormals, signed zero and infinities. There is no FP-state requirement, and execution does not modify the caller's floating-point environment.

Tile order is C/D/H/W within each logical outer slice; pixel order inside a tile is D/H/W/C. Boundary tiles use actual spatial/channel extents. Each tile's complete byte span is rounded up to 16 bytes. PadTo16 rounds the channels of each tile independently.

For BF16 shape [2,17] with W/C mapping and tile [1,1,2,16], Compact needs 80 bytes: 64 for the first C16 tile and a 4-byte tail payload plus 12 alignment bytes. PadTo16 needs 128 bytes. Never infer tiled capacity from logical element_count × dtype_width alone.

C++ call​

Place the includes and namespace aliases at file scope; the remaining statements belong in a simaai::kernels::Status-returning caller function. input_views and output_views are caller-supplied arrays of ConstHostBuffer and HostBuffer in port order, with accessible capacities and alignment from the checked plan. Keep their storage alive until synchronous execution returns.

#include <array>
#include <simaai/kernels/a65/detess.h>

namespace k = simaai::kernels;
namespace op = k::a65::detess;
k::MlaTiled layout;
layout.axes = {-1, -1, 0, 1}; // Logical shape [W,C], explicit channel axis.
layout.tile_shape = {1, 1, 2, 3};
const k::TensorSpec linear{{2, 3}, k::DType::BFloat16};
const k::TensorSpec tiled{{2, 3}, k::DType::BFloat16, layout};
const std::array inputs{tiled}, outputs{linear};
auto checked =
    op::check_inference({inputs, outputs, {}});
if (const auto *error = std::get_if<k::Error>(&checked)) return *error;
const auto &plan = std::get<op::Plan>(checked);

return op::execute(plan, input_views, output_views);

See the correctness tests (A65/detess/tests/correctness.cpp) for concrete storage, independent expected results and failure cases.

The correctness tests use independent physical-byte goldens; a successful round trip alone does not prove the layout correct.

Memory and lifecycle​

check_inference() validates metadata and returns owned immutable metadata; A65 preparation selects the row path. No request spans are retained. execute() validates actual bindings before any write and runs synchronously without heap allocation, a full-tensor intermediate, or private worker threads.

Allocate from the plan's physical requirements: the linear side needs scalar alignment, the tiled side 16-byte alignment. Binding capacities describe real accessible storage, including strided spans or tile padding. Disjoint views of one allocation are permitted; intersecting accessed bounding spans are rejected. There is no in-place guarantee, even for apparently identical byte order.

Callers retain A65 storage until return. Runtime owns allocation/mapping, coherency and asynchronous submission/retirement, retaining EV74 storage until device completion. A shared plan does not make shared writable buffers safe.

Implementation notes​

Preparation chooses INT8/BF16 and contiguous-channel/scattered-channel rows. Contiguous INT8 spans use bounded copies. BF16 uses integer NEON byte split/join, including C2/C3 width-vectorized paths and 16-/8-channel groups; short/scattered tails use bounded scalar byte accesses. Compact BF16 C1 needs no byte rearrangement and can copy directly. All vector accesses remain inside the declared span.

Channel-only inputs bypass multidimensional coordinate traversal; other shapes reuse the common prevalidated tile geometry. No generic dtype dispatch occurs inside per-element loops. Tiled gaps and output strides are handled in the same pass, not by a tensor-sized repacking buffer. These are implementation choices, not an unmeasured speedup claim.

Tests and qualification​

One generic correctness executable covers 300 deterministic shapes across all six ranks for each dtype, exhaustive INT8/BF16 bit patterns, independent physical goldens, mapped-axis permutations, pitched/permuted strides, padding, invalid requests, exact-capacity protected tails, reuse and FP-state independence. The separate default-enabled latency executable measures checked calls and records preparation separately, across dense and strided small/large shapes.

Host-scalar checks do not qualify A65 NEON or real EV DMA. Real-device execution and latency acceptance must be reported separately. Neither the broken extracted standalone EV implementation nor Tess/Detess round trips are the sole oracle. See build and qualification.