Preproc memory and execution

The kernel stages bounded source rows and writes the final output layout directly. There is no full-frame resize or RGB intermediate in DDR. The sections below explain packet ownership, local storage, DMA overlap and the conditions that select each implementation family. They describe the current implementation, not a stable dispatch ABI or a measured performance guarantee.

Read the call contract and ordered mathematics first. Use validation and measurement for runnable checks and acceptance policy.

Find an implementation family

Start with the numerical contract in ordered computation. This page explains how each family preserves that result while reducing data movement or repeated work. Eligibility is based on geometry, dtype and storage—not a particular benchmark shape. Ineligible inputs stay on a checked fallback.

Family	Eligibility and benefit	Fallback / details
General row/panel workers	Bounded staged rows and uniquely owned output granules	Invocation and completion, row arena
Exact 2× YUV	Proved resize ratio; fewer taps and bounded tile strips	General sampling; tile strips and Compact bands
Fractional Bilinear INT8	Separate compilation keeps unrelated branches out of hot workers	Other dtype/geometry workers; compilation boundary
Packed Bilinear INT8	Packed image sampling and final-byte conversion	General sampling; packed implementation
Bicubic / BoxAverage	Bounded tap reuse or exact-domain arithmetic	Ordered FP contract; sampling implementations
Identity / Nearest INT8	Byte-domain sampling where the conversion contract permits it	Existing general paths; byte-domain sampling
ROI lists	One submission; bounded virtual rows and explicit unused-slot clearing	In-frame crops use ordinary workers; ROI-list execution

The linked sections give the complete predicates, memory bounds and tails. This index is navigation, not a second dispatch specification.

Invocation and completion

Native Preproc ABI 4 keeps a 256-byte ordinary packet and existing address slots. ROI batches use a second exact size, 2056 bytes, containing up to 50 fixed-width 36-byte source/destination records after the base header. Ordinary invocation copies only its active 256 bytes; the extension is not extra hot-path traffic. It names the formerly reserved words at offsets 176 and 188 as three row pitches and three frame pitches, respectively. Offsets 200 and 204 hold the ROI count and source batch for extended packets and remain zero otherwise. Unused plane fields, records and reserved words remain zero. Host and device repeat pitch, overflow and input/output overlap validation. Version4 additionally admits unsigned one-byte tiled output without changing the packet sizes, address slots, numerical workers or tile packing. The native entry is simaai_kernels_ev74_preproc_v4; old firmware must fail the capability handshake, not interpret the new packet. Discovery probes the maximum 2056-byte size, proving list-capable firmware before admitting either packet kind. Rebuild host package and firmware together. The decoded control and each OpenCL family share asserted field offsets. Only global source address generation changes; ROI staging, SIMD arithmetic, rounding, specialization selection and dense-output writes are unchanged. Pitched planes use the same bounded row-DMA paths as dense planes.

The EV host codec creates a versioned relocatable packet; C++ Plan objects are not serialized directly. Runtime retains every plane owner and output owner, performs coherency/relocation, submits the native entry, and retires resources only after completion. A synchronous call is submission followed by waiting; submission returning is not permission to reuse input or output memory.

Output starts at a 16-byte-aligned address, including dense output. With the Runtime adapter, use a different backing allocation for output than for any input plane—even when byte ranges would be disjoint. Shared input planes use disjoint views of one owner; Runtime acquires its read access once while retaining all mapping leases. Separate owner wrappers are not automatically merged solely because they refer to the same allocation.

Workers own disjoint 16-byte output DMA granules. In the general implementation, a regular tiled path traverses logical rows across tile columns and uses pitched output DMA. If a tile row is not individually 16-byte aligned, it groups 16 / gcd(tile_row_bytes, 16) rows into an aligned band. For example, a compact INT8 C3 tile eight pixels wide has 24-byte rows and uses two-row bands. The local writer places each row's pixels in the requested tile-major band records; it does not relabel the output layout.

This path requires at least one complete band per interior tile and a band that fits the bounded output slot. It retains floor(tile_height / band_height) complete bands even when the tile ends with fewer rows. Each full tile owns its remaining rows and rounded tile-end bytes as one exact aligned panel interval; right and bottom partial tiles retain their original complete physical extents. No tail is appended to a neighboring band or tile.

Workers partition active-image and padding-only complete bands separately. Their live-rectangle boundaries use tile coordinates: the complete-band index at row y is floor(y / tile_height) * bands_per_tile plus the clipped within-tile band index (rounded upward for the exclusive end). A band crossing a destination boundary stays intact in the active partition. Full-tile tails and partial edges form a separate exact-panel pool. Whole-band/tail ownership prevents different workers from sharing an output DMA granule; every pending copy retires before slot reuse and return. Tiles shorter than one band retain whole-image panels.

A physical tile's total extent is a software offset, not necessarily a hardware 2D pitch. The ordinary general renderer retains cross-column bands for tile extents above 65,535 bytes when at least two complete W tiles and one complete H tile exist. It publishes each owned W-tile band as a bounded 1D copy at its full-width destination offset; it never truncates or widens the descriptor's 16-bit pitch fields. Other workers and ineligible geometries retain their existing paths.

Compact output also groups two rows when the complete two-row canvas fits the current output slot. For oversized physical tiles with individually 16-byte-aligned tile rows, two-row bands additionally require an even tile height, a tile row of at most half that slot's capacity and non-Box interpolation. Fixed-resource workers retain their original 4 KiB slot and 2 KiB row bound. Those samplers request at most eight source rows across the pair, within the existing row cache. This changes traversal and publication, not sampling or rounding. BoxAverage and wider or odd-height tiles keep their previous band height.

Every 1D copy in a strip links to its predecessor. Each of the two local output slots retains the strip's tail event, which is waited before rewriting the slot and again before return. Completed requests recycle through the SDK's bounded descriptor ring; a tail alone would not retire earlier unlinked transfers. No image-sized staging allocation or output read-modify-write is introduced.

Typed masked SIMD writers pack complete pixels directly. Dense 16-bit output uses interleaved scalar bytes; compact MLA BF16 instead stores each pixel's low channel bytes followed by high channel bytes. PadTo16 writers fill ghost channels and scatter only the real channels. Only physical-panel fragments need scalar byte-coordinate decoding. Constant canvas padding is converted once per worker and repeated as final bits; destination validity is never cached.

Ordinary row arena and output windows

The ordinary worker reuses the original 106,496-byte row/output allocation; it does not allocate a larger VCCM arena. Absolute source-X indexing requires space for the full source width, not only the cropped ROI. The aligned row pitch is:

row_pitch = round_up(source_width * local_bytes_per_x, 16)
local_bytes_per_x = 3 for RGB/BGR, 1 for Gray, at most 2 for YUV

Eight cached rows keep their original tags, tap ownership and replacement policy. The ordinary NV12/NV16 fractional-Bilinear map path reserves a separate 8 KiB region when it is admitted. Two disjoint output windows use the remaining space:

capacity = round_down(min(32768,
    (106496 - 8 * row_pitch - map_bytes) / 2,
    physical_output_bytes / (4 * workers)), 4096)

[ eight compact rows ][ optional two X maps ][ output 0 ][ output 1 ][ unused ]

A useful full Bicubic X-weight map can reserve its bounded bytes before choosing these output windows when it would not fit the unused suffix. Admission proves that the smaller windows still hold the same complete full-width bands: no partial H/W edge, extra strip or unrepresentable publication pitch is introduced. Otherwise the original window sizing and literal polynomial fallback remain.

Only a capacity greater than 4 KiB activates this arrangement. Otherwise the worker retains its original eight 12 KiB rows, map-tail addresses and two 4 KiB output slots. The Gray worker uses its own smaller allocation as described below. Fractional RGB-cubic and the other specialized workers retain their fixed-resource allocations; the RGB-cubic four-byte packed-row expansion is not part of either ordinary or Gray arena. The packed fractional-cubic worker reserves eight 11 KiB rows, admitting RGB/BGR ROI intervals whose absolute exclusive X end is at most 2816. A wide source pitch does not enlarge the local footprint: only the sampled ROI union is transferred, then expanded in place from three to four bytes per pixel. Larger absolute ends retain the ordinary sampler. The joint sampler keeps the same four-by-four tap order, per-channel FP32 sums and final conversion; its larger row allocation stays inside the existing 128 KiB worker allocation, including compiled frames and the SDK call allowance.

Interior bands and compressed edges can fill a larger window before publication. The physical-panel fallback still partitions the original 4 KiB owner intervals; it coalesces only bytes within that worker's interval and copies the exact final extent. This preserves disjoint 16-byte output DMA granules even for a short last interval. Input row pitch, cached sample coordinates, HALF operation order, BF16 conversion, constant padding and typed storage do not change.

Each output window is overwritten only after its retained DMA tail retires, and both tails retire before return. Source rows, numerical maps and either live output window cannot borrow one another's storage. The pure scalar output-cursor and owner-partition helpers receive only immutable control or scalar geometry; they do not receive DMA events, source rows, output slots or SDK launch state.

The general implementation stages packed source ROI windows in an eight-slot, per-worker VCCM row cache, preserving full-source chroma addressing. Before replacing a slot, the loader pins every cached row required by the next footprint. It uses invalid slots before evicting valid rows, then selects unpinned victims in round-robin order. Repeated clamped border rows share one slot, and batch changes invalidate the row tags and replacement cursor. A private tap-to-slot map keeps numerical tap order independent of replacement order; it does not reorder arithmetic. Cache state never survives the invocation or assumes that a caller's image is unchanged. Resource-specialized paired-row readers stage NV12/I420 chroma with its corresponding cached luma row; they have no independent chroma-row cache. Distinct luma rows can therefore load the same source chroma row. This keeps one bounded tap-to-slot map and preserves odd ROI phase and the different NV16 vertical addressing rule.

Ordinary YUV requests retain separate eight-entry luma and chroma row tags in the same bounded source arena. Chroma identity survives luma eviction; required UV rows are pinned before choosing victims, and all plane DMA retires before sampling. Batch/ROI-span changes invalidate both rings. NV12/I420 can reuse a chroma row across two neighboring luma rows; NV16 preserves its independent row identity rather than pretending to have subsampled vertical chroma. Other resource-specialized leaves retain their original paired-row readers. This changes transfer reuse, not HALF sampling, signed color conversion or output packing.

The ordinary and fixed-Gray readers also cache the last sampled X bounds within the worker invocation. A full-ROI request needs no coordinate preparation; a repeated narrow request reuses bounds only when its X origin and pixel extent are identical. Geometry and ROI are immutable during that invocation, and the 13-bit fields include every safe SIMD tail lane. The cache still compares these bounds with the current row footprint: another internal map owner can change that footprint, requiring row-tag invalidation even when the request repeats. Only two scalar words are retained; no source pixels, pointers, DMA events or cross-invocation state are cached. Dense and other resource-specialized readers keep their existing paths.

A private, immutable worker context prepares coordinate ratios, exact integer ratio predicates, color coefficients and applicable half-precision coefficient bit broadcasts once per invocation. It is not a new public parameter object or device cache. Raw canvas-padding values and their output conversions are prepared only when the destination rectangle leaves canvas pixels uncovered; tiled channel padding and alignment bytes remain governed by their separate storage rules. Interior pixel groups avoid canvas-padding blends; mixed boundary groups retain the exact bit-select behavior, and inactive SIMD tail lanes still use safely clamped coordinates. Constant padding is converted without constructing sampling geometry.

Numerical work uses 16-lane SIMD. Output DMA slots are double-buffered. For each regular band, first-row source staging precedes output-slot retirement, allowing input DMA to overlap outstanding output DMA. Source-row loads are explicitly waited before computation; this is not input-DMA/compute overlap. Dense and MLA output are written directly without an image-sized intermediate DDR tensor. Per-operation local scratch is not a general allocator or a separate scheduler.

Separately compiled exact-2× PadTo16 implementations

One native entry selects an internal implementation after normal admission. The public request, packet, asynchronous submission/completion and allocation ownership are unchanged. Each implementation has a lazily created kernel handle; selection uses validated tensor facts, not model names or benchmark dimensions. After checking the packed bilinear INT8 implementation described below, PadTo16 requests select one format/dtype family and check its shared geometry rules. Other requests retain the general implementation. There is no per-pixel implementation dispatch.

Input	Output	Internal source
Gray	Gray INT8	ocl_native_preproc_gray_i8.cl
Gray	Gray BF16	ocl_native_preproc_gray_bf16.cl
RGB or BGR	RGB or BGR INT8	ocl_native_preproc_rgb_i8.cl
RGB or BGR	RGB or BGR BF16	ocl_native_preproc_rgb_bf16.cl
NV12, NV16 or I420	RGB or BGR INT8	ocl_native_preproc_yuv_i8.cl
NV12, NV16 or I420	RGB or BGR BF16	ocl_native_preproc_yuv_bf16.cl

These implementations require bilinear resize with the ROI exactly twice the output width and height, a full-canvas destination, and PadTo16 storage. They also require complete tiles, a physical tile line fitting the 4 KiB output slot, a tile pitch no larger than 65,535 bytes, and at least as many batch/tile-row tasks as active workers. Other requests retain the general implementation, including partial tiles, canvas padding and fractional ratios, unless they qualify for the separate packed bilinear INT8 implementation. native_preproc_select.h owns these private selection boundaries.

Each source contains only its required arithmetic and two-row source staging, not copies of the general interpolation machinery. Two source-footprint slots alternate: the next output row's required source rows are issued into the other slot before computing the current row. A slot is read only after its input DMA events retire, and it is not overwritten while its computation is active. The final row does not prefetch beyond its tile-row task. YUV footprints retain odd ROI chroma phase and NV16's distinct vertical sampling. This bounded overlap changes transfer scheduling, not interpolation or arithmetic order. It applies only to these separately selected exact-2× workers; the general row cache keeps its existing synchronous source staging.

Full Gray SIMD groups use aligned adjacent-byte pair loads; tails use bounded gathers. RGB uses packed halfword gathers and reconstructs semantic R/G/B sums before applying affine coefficients. Input BGR order and output BGR order remain independent.

For four U8 samples, the integer sum is in [0,1020] and its quarter average is exactly representable in FP16. Consequently:

• INT8 Gray/RGB: the required U8 round-toward-zero stage equals sum >> 2. The shared native_preproc_quant.h then preserves the existing three separate FP16 operations: subtract the offset, multiply by the affine multiplier, multiply by the quantization multiplier. INT16 saturation/truncation, zero point addition and INT8 clamping remain unchanged. Multipliers are not merged.
• BF16 Gray/RGB: keep fractional quarters. Convert the integer sum to FP32 and multiply by 0.25f, then perform the separately rounded FP32 subtraction and multiplication. Truncate the resulting FP32 bits to BF16 as before; do not use the INT8 path's integer truncation.
• YUV INT8: preserve source-coordinate chroma phase. The second horizontal chroma sample is needed when the ROI X origin is odd. NV16 needs both chroma rows; NV12/I420 need the second row when the ROI Y origin is odd. Average each component, truncate as required by color conversion, apply the same integer matrix coefficients and saturate to U8 before shared INT8 quantization. The intermediate integer RGB values fit exactly in FP16, so omitting their half round trip does not change the subsequent saturated U8 values.
• YUV BF16: use the same component averaging/truncation and integer color matrix, but retain signed RGB values; do not apply INT8's U8 saturation. Matrix results in [-238,491] are exact in FP16, so direct INT32-to-FP32 conversion equals the general half-to-FP32 sequence. Apply each semantic channel's FP32 subtraction and multiplication separately, then truncate to BF16. Both byte planes use the requested RGB/BGR storage order.

Each worker initializes its two local output slots' ghost channels once per invocation. Every live channel byte is overwritten before each DMA; ghost positions never change within these full-tile PadTo16 slots. This does not cache or trust caller-owned output bytes. BF16 writes each channel’s low byte at its pixel channel offset and its high byte at that offset plus 16, leaving ghost channels in both byte planes zero. INT8 ghosts contain the current invocation's encoded zero point.

The retained row paths own complete tile rows. Eligible YUV paths instead own complete physical tile strips, as described below. Both wait for source DMA before sampling and retire each output slot before reuse. The smaller implementations avoid general row-cache and format-dispatch work; this is an implementation optimization, not a new mathematical contract. Separate compilation isolates code generation but does not guarantee unchanged linked addresses or latency in other paths.

Bounded exact-2× YUV tile strips

The INT8 and BF16 PadTo16 YUV implementations share only cold footprint and DMA-view helpers in native_preproc_yuv_windows.h; their existing numerical loops remain separate. A tile strip is admitted for power-of-two width tiles whose full physical extent fits a 32 KiB output slot and whose Y/U/V footprint fits one 16 KiB source slot. Final partial H/W tiles retain their actual extents: their source slab, tile pitch, byte-plane offset and output length are derived from those extents rather than switching the whole image to the row fallback. All source row pitches must fit the DMA 16-bit field. Other admitted geometries retain the original two-row path; the BF16 odd-integer-ratio sampled-row path is unchanged.

For a strip of P output pixels and tile height T, let x and y be the ROI origin's parity. The luma slab has width 2P and height 2T. The chroma slab has P+x samples per row and 2T rows for NV16, or T+y rows for NV12/I420. Source slots round local plane pitches up to16bytes; global source pitches are never rounded, truncated or copied as payload. I420 stages U and V separately. Thus source capacity is checked against the actual plane rectangles, including odd-phase chroma neighbors, not the source image's full-row width.

Two disjoint16KiB slots occupy the existing32KiB input arena. Each worker partitions the actual strip tasks, waits for all current-plane reads, then prefetches the next owned strip into the other source slot before sampling. A worker with only one strip has no future input DMA to overlap. Two32KiB final output slots contain whole physical tiles, published with one contiguous1D copy per strip. They retire before reuse and before return. No image-sized scratch or speculative source access is introduced.

The tile visitation changes no numerical or layout rule. INT8 packs the final R/G/B bytes and the already-owned fourth ghost byte into one aligned32-bit store per pixel; the ghost retains the current encoded zero point. BF16 packs low/high R/G/B bytes into two aligned words, with their fourth bytes zero. All remaining ghost bytes are initialized once per invocation. These stores cannot overwrite a neighboring pixel, an application hole or another worker's DMA granule; no output read-modify-write is needed.

Exact-2× vertical-letterbox YUV INT8

ocl_native_preproc_yuv_i8_letterbox.cl is a separate compilation context for NV16, NV12 and I420 bilinear INT8 RGB/BGR output with PadTo16 storage. Selection requires a full-width destination at X=0, a nonempty active height smaller than the canvas, and ROI width/height exactly twice that destination. Power-of-two tile widths, exact physical tile sizes and representable plane pitches must also satisfy the shared bounded-window proof. The selection has no camera-size, model-name, coefficient-value or 640-pixel special case; fractional ratios, other storage and ineligible geometry retain their existing paths.

Each window owns complete physical tiles, including compressed right/bottom edges. Its active rows are the intersection with the destination. Source Y starts at roi_y + 2 * (window_y + first_active_row - destination_y); padding-only windows issue no input transfer. NV16 stages both distinct chroma rows for each output row. NV12/I420 retain their vertical subsampling and absolute odd-ROI phase. No pitch holes, neighboring source pixels or uninitialized local padding are treated as image data.

The existing exact integer four-tap averages and color conversion still reach the same UInt8 boundary. Each worker constructs its channel's 256-entry table using the unchanged separately rounded FP16 subtract, affine multiply and quantization multiply, then the original saturation, truncation and zero point. Equal prepared half coefficient bits share tables; approximate FP32 equality is not used. Canvas padding passes through the same conversion, while physical PadTo16 ghost bytes remain the encoded zero point. Caller-output contents are never reused as an initialization promise.

Two input slots of at most 20 KiB and two output slots of at most 40 KiB overlap next-window input with current computation and publication. A larger group with a less-than-half-filled final X strip retains the compact 16/32 KiB transfer geometry. Windows are cycled across dense workers; when X-window count and worker count share a factor, complete tile rows are cycled instead, so a narrow last strip cannot occupy entire workers. These are metadata decisions, not per-pixel dispatch or a tensor-sized task list. Every DMA event retires before its slot is consumed/reused or its worker returns. Compiled frames, tables, private descendants and SDK/alignment allowances still require the normal per-worker and shared-VCCM resource gates.

The existing correctness executable exercises this owner with all three YUV formats, RGB/BGR ordering, both matrices, odd ROI phase, pitched/batched inputs, nonuniform affine/padding values, partial tiles, dirty output and one through four workers under immediate/deferred DMA. The camera panel includes NV16 720p square-model requests, different tile geometries and smaller/larger siblings. These tests preserve independent numerical/layout goldens; host expression models do not replace real-device qualification.

Exact-2× Compact YUV bands

The ordinary general worker can reuse exact256-entry UInt8 quantization tables for INT8 output. Sampling retains its ordered HALF results. The ordinary YUV path's fixed-matrix colors lie in [-238,491], where conversion to HALF is exact. Interior groups therefore clamp that same signed integer directly to UInt8 before lookup, omitting only the redundant color HALF round trip. Non-YUV samples, mixed canvas boundaries and short INT8 work retain their original HALF conversion path. Each entry uses the original separately rounded HALF subtraction, affine multiply and quantization multiply, followed by the same INT16 saturation/truncation, zero-point addition and INT8 clamp. Raw offset/multiplier bit keys alias equal semantic-channel tables; signed-zero keys remain distinct. Tables are rebuilt per invocation before canvas padding, with768bytes of per-core static local storage, not an automatic-stack or DDR allocation.

Setup requires total active pixels of at least512times the selected worker count. This is an average-work heuristic, not a guarantee for every worker; padding-only workers can build tables too. Short jobs keep the original ordered arithmetic through a shared private pure-arithmetic leaf. Physical ghosts, output holes, source reads, DMA event lifetimes and all non-INT8 rounding rules remain unchanged. Interior YUV UInt8 output uses the same integer clamp. BF16/FP16 output keeps signed colors, converts them directly to FP32, subtracts and multiplies separately, then applies the original BF16 truncation or FP16 nearest-even conversion. The shared final-color helper accepts only the exact color, scalar coefficients and an optional local lookup table—not an SDK/event context. Mixed padding retains bit-select semantics.

The ordinary and fixed-Gray workers reuse the already-prepared HALF X fraction instead of constructing another HALF zero for each group. BoxAverage prepares positive zero once; Identity does not consume the fraction. Other interpolation modes overwrite it with the same integral phase or fractional sampled weight as before. Sampling, positive-zero bits and all rounding are unchanged. These finite-domain and preparation changes do not establish a latency bound.

The separate Compact INT8 worker preserves the same exact-2× YUV equations. It requires complete tiles, a full-canvas destination, a power-of-two tile width, an aligned output address and complete 16-byte-owned bands. The staged ROI is at most 4096 luma bytes wide, with at most 2048 chroma samples after rounding the absolute ROI endpoints. An odd ROI origin therefore needs its extra chroma sample; NV16 keeps both distinct full-height chroma rows.

The worker selects a power-of-two band height of at most 16 rows that divides the tile height and fits one 32 KiB final-output slot. Its two output slots are unchanged. The two source-footprint slots use a flat 32 KiB allocation: each source row reserves 4096 luma bytes and 4096 chroma bytes, or two 2048-byte U/V regions for I420. Consecutive rows use an exact 2D read only when its source pitch is representable; otherwise each actual row uses an exact 1D read.

A total physical tile larger than 65,535 bytes retains its full 32-bit software offset. The writer uses linked 1D copies of complete owned tile bands instead of widening the hardware 2D pitch. The representable 2D path stays unchanged. Each slot's retained tail event retires the whole linked chain before reuse and return.

For representable source-plane pitches, a bounded tile-X/tile-H slab can reuse that same 32 KiB input allocation. Its height is the largest complete owned band fitting both source planes (including odd-origin chroma halo and aligned I420 V origin) and one unchanged output slot. Admission requires fewer combined input and output descriptors than the original row pipeline. Absolute source coordinates are rounded before constructing local plane views; NV16 retains both chroma rows. A slab drains all input events before sampling and publishes one contiguous physical tile band; the final short band retains complete DMA granules. Workers partition the actual slab tasks, including two/three-worker rings. Source-pitch, footprint or descriptor-cost counterexamples keep the original prefetched-row pipeline. No full frame, extra arena or output read is introduced. Descriptor reduction alone does not establish latency improvement. Partial tiles, fractional resize, canvas padding and ineligible band extents retain their existing implementations.

Ordinary row rectangles and fractional YUV geometry

The ordinary reader groups newly missing consecutive source rows only when those rows also occupy consecutive physical ring slots. One representable 2D read then replaces their exact 1D reads. Existing hits, repeated clamped taps, ring wrap and unrepresentable source pitches retain the exact copies. Each plane independently uses its real pitch, ROI/chroma origin and row identity; NV16 never uses NV12's half-height chroma coordinate. A rectangle contains at most32KiB, has a positive source pitch at most65,535bytes, and stays within the original row arena. One inlined launch loop serves packed RGB/BGR, Gray and the YUV planes: SDK launch/event state never crosses an outlined helper. All input events retire before sampling; publication and output-slot retirement are unchanged.

Paired NV12/NV16 Bilinear sampling also covers integral ratios. For UInt8 samples, every midpoint and quarter is exactly representable in HALF:

$$\tfrac{a+b+c+d}{4} = \operatorname{half}\left( \tfrac{a+b}{2}+ \tfrac{\frac{c+d}{2}-\frac{a+b}{2}}{2}\right), \qquad a,b,c,d\in\{0,\ldots,255\}.$$

Thus the existing separately rounded HALF interpolation preserves the integral sampler's integer-sum/FP32-scale/HALF result exactly, while one bounded chroma pair gather supplies both U and V. It does not average converted RGB colors or move color conversion before raw-plane sampling.

A positive integral X ratio permits omission of repeated chroma taps when its canonical full-source positions share a pair: odd ratios already use one tap; for even ratios the first tap parity is (roi_x + (ratio_x - 1) / 2) & 1. Zero parity proves that both taps address the same pair in every active and tail-clamped lane. Ordinary I420 uses this same proof for its separate U/V planes. Its independent chroma cache additionally omits a vertical blend only when both tap offsets identify the same initialized chroma slot. Fractional X geometry and distinct cache slots keep all original taps. Padding, source bounds, typed conversion, physical stores, DMA ownership and event retirement are unchanged; no image data is reused across invocations.

The ordinary worker reuses bounded X maps for fractional Bilinear RGB/BGR, I420 and NV12/NV16, and for Nearest with a nonintegral X ratio. Their original fixed row-tail regions are each 4 KiB. Map admission requires the existing source-row reservation to fit within 8 KiB: RGB/BGR reserves three bytes per pixel; YUV reserves two, including planar YUV's conservative row capacity. Wider rows retain the original sampler. With the original 4 KiB output slots the maps reuse the otherwise-unused tails of the first two 12 KiB row slots at their original offsets. With larger output windows they follow the eight compacted source rows in the same allocation. Each map then reserves only its complete entry bytes rounded to 64-byte alignment; the fractions follow the index span, and both output windows follow the two maps. No source DMA or gather reaches either map. The first map records independently clamped tap0 and a0/1 tap delta in bit12; the second retains every canonical HALF fraction bit. Maps cover the complete canvas plus every inactive16-lane tail and are rebuilt before each invocation's first source DMA. Their contents remain immutable until that worker returns.

A map needs round_up(output_width + 15, 16) ushort entries per 4 KiB region, so2033pixels is the largest admitted canvas width. Setup also requires at least512active pixels per selected worker on average. Fully integral Bilinear axes, integral-X Nearest, short work and larger canvases keep the original sampler. The map preserves ((dx + 0.5f) * ratio_x - 0.5f), its signed floor, independently clamped taps and HALF nearest-even fraction. Nearest uses only the clamped first index; its map fractions are initialized but not consumed. Interpolation, color, affine, quantization and final storage retain their original ordered equations. Specialized and Gray workers remain unchanged. This is invocation-local reuse of geometry, not caching image samples or reusing a previous output's initialization. Reduced descriptor/geometry work alone does not establish a latency improvement or a universal1ms bound.

Fractional Bilinear INT8 compilation boundary

When no earlier dedicated worker applies, a private INT8 owner handles ordinary three-channel, non-Gray Bilinear images with fractional ratios on both axes and an output width at most 2048. It shares the canonical row cache, prepared X maps, output slots, physical writers and DMA retirement; it is not another public operation or a shape-specific dispatch list. Maps retain their own capacity and work-size admission described above. Unmapped groups use the original sampler.

For an admitted map, the two X taps are already independently clamped. YUV sampling gathers them directly in full-source luma/chroma coordinates, preserving odd ROI phase. RGB/BGR sampling loads one aligned local halfword wholly inside each three-byte pixel and gathers its remaining byte separately. Odd local row bases keep the byte-gather fallback; no DDR transfer is widened. Horizontal and vertical HALF subtraction, multiplication and addition boundaries are unchanged. Keeping this owner separate lets the compiler prune unrelated interpolation and output-conversion state without expanding the general worker's hot code.

Packed bilinear INT8 implementation

ocl_native_preproc_packed_i8.cl handles RGB/BGR input and RGB/BGR INT8 output for arbitrary bilinear ratios, including ROI and canvas padding. It requires a source ROI width at most 2048 and a 16-byte-aligned output address. Dense bilinear output retains aligned rows. Dense Identity may instead group adjacent bounded bands until their combined byte span is16-byte aligned; every sub-band in a group belongs to one worker. An unaligned final group has one writer, and multiple frames are admitted only when their starts retain the same DMA phase. Compact MLA output uses a power-of-two tile width, a tile pitch at most65,535 bytes and bands with exclusive16-byte DMA ownership; bounded final partial H/W tiles use the existing actual-extent publisher. ROI-list execution, PadTo16, other dtypes and ineligible geometry retain their existing implementations; these are private selection limits, not narrower public admission limits.

The implementation selects a power-of-two band height of at most 16 rows, bounded by the 32 KiB output slot and, for tiled output, the tile height and DMA ownership alignment. Cyclic band assignment distributes canvas and active-image work without assigning whole tile rows to individual workers. Four bounded source-row slots retain the current bilinear taps while the next row's input DMA is issued. Each read retires before sampling; pinned taps cannot be overwritten by the prefetch. Two output slots retire before reuse, and all output DMA retires before return. No image-sized intermediate is allocated.

The bounded window leaf holds up to2048 output X positions using two16-bit maps: the first RGB byte index carries one checked neighboring-tap bit, and the other map retains the exact HALF fraction. The neighboring tap is either the same clamped pixel or the next three-byte pixel. This replaces a redundant index map without changing source bounds or interpolation. The full-row leaves retain their original smaller maps and on-the-fly fallback. Four source-row slots and two output slots retain their original allocation budgets.

Sampling retains the separately rounded half-precision bilinear lerps, U8 saturation/truncation, and the three ordered half-precision affine/quantization operations. Per-row Y geometry and coefficient broadcasts are reused; final channel vectors are written directly into the dense or compact output slot. Input and output BGR permutations remain independent. The implementation does not fold multipliers, lower interpolation quality or change physical tensor storage. Complete padding-only Dense/Compact bands with nonuniform RGB padding repeat their already-encoded three-byte pattern using three16-byte vectors per 48-byte period. Input/output BGR order is applied before repetition; partial bands and active/mixed image boundaries retain the masked writer. Uniform padding keeps its existing wide fill. This skips sampling and per-pixel stores only for bands already proved wholly outside the destination. Selection and source structure alone do not establish device latency.

Pitched-plane coverage and storage

The existing Preproc correctness executable also compares padded RGB/BGR/Gray, NV12, NV16 and independently pitched I420 planes against dense independent oracle inputs. It covers ranks 3–6, batch stepping, all four output scalar types, the six specialized INT8/BF16 tiled paths, immediate/deferred modeled DMA, and exact final-row capacities. Malformed pitch and overflow packets are rejected before dispatch. These host expression tests validate addressing and numerical equivalence, not EV ISA or latency; the matching firmware cohort still requires private compilation and real-device qualification. The ROI fixtures independently materialize raw virtual images only in test memory, including extreme outside origins, invalid/overflow counts, reordered source frames, tail zeroing and explicit empty lists. The real-device fixture contains the same pitched and ROI cases. These source tests do not replace private compilation, device correctness and matched latency qualification of the exact firmware being shipped.

Dense ROI frames whose output address is not 16-byte aligned use one EV worker. This prevents adjacent output panels from sharing a physical DMA write granule; aligned frames retain the normal worker selection. The same rule applies to the binary-zero unused tail.

The fixed-Gray worker retains all eight absolute-index source rows and its original 40,960-byte allocation. When short source rows leave useful space, two disjoint output windows reuse only the unused row tails:

row_pitch = round_up(source_width, 16)
capacity = round_down(min(32768, (40960 - 8 * row_pitch) / 2,
                          physical_output_bytes / (4 * workers)), 4096)

Capacity greater than 4 KiB uses the compacted row pitch and two larger windows; otherwise the original eight 4 KiB rows and two 4 KiB outputs remain. The tap ring is never shortened, and Gray has no X-map reservation in this arrangement. Only already-owned physical intervals are coalesced; the same complete bands, edge extents and 16-byte output ownership rules apply. No additional input bytes or source-row rereads are required by this storage change.

The Gray worker preserves its physical output-panel traversal. For tall multi-W-tile walks whose active source working set does not fit the row ring, it stages the same exact sampled-X span as the ordinary worker, including inactive SIMD tail taps and clamped borders. The bounded scalar footprint calculation is shared through a private C-linkage metadata-only helper; source coordinates, separately rounded FP32 arithmetic, sampling, padding and DMA event retirement are unchanged. Fitting-row, whole-W and vertical-upsampling neighbors retain full-ROI staging. No image-sized scratch or new input permissions are introduced.

Ordinary Pad16 local ghost reuse

For full-canvas Pad16 C1/C3 requests, the ordinary renderer initializes both owned output slots once per invocation only when the current worker owns at least twice its current output-slot capacity in proved complete-pixel clearing work. A conservative count omits compressed edges and the global final panel; it is not a measured optimal crossover. Padding-heavy or shorter workers retain the original group clears. Their 16- or 32-byte physical pixel sizes divide every clipped tile extent and current 4 KiB-multiple panel step, so live channel and ghost byte roles cannot exchange when a slot is reused. Final H/W tiles retain their real compressed geometry; no unowned output holes are initialized.

Every dynamic live channel, including numerically transformed canvas padding, is overwritten before publication. Ghosts use the current INT8 zero point or zero for other output dtypes; no state survives between invocations. Other writers, non-Pad16 layouts and unaligned fragments retain canonical exact-byte initialization. The output traversal, transfer sizes, events and waits are unchanged. This removes repeated local ghost clearing, not mandatory DDR padding traffic.

Bounded cubic tile-local geometry

The fractional-cubic entry is admitted only for RGB/BGR input and RGB/BGR C3 output. Its private input-format accessor preserves the requested RGB versus BGR byte order while excluding Gray/YUV loader branches from that entry. Other input formats retain their existing workers. This specialization does not change tap selection, maps, weights, accumulation order or conversion.

Fractional RGB/BGR cubic requests with oversized tiled payloads may reuse the existing 1040-entry X geometry arena for one actual physical tile at a time. The original full-width mapped route remains first. A conservative per-worker complete-live-tile work bound admits the additional mode; small jobs, dense storage, mixed destination canvases and unproved clipped-height work retain the original sampler. Maps include the clipped last tile and every inactive SIMD lane, with the original full-canvas coordinate clamp, signed floor and ordered FP32 cubic polynomial. No weights or sampling sums are reassociated.

The tag records the tile origin within the immutable invocation geometry, independently of the source ring's batch and row tags. Input rows use the completed map endpoints to stage the exact clamped cubic X tap union. A changed span invalidates resident row tags only after prior transfers have retired; an ROI that fits the existing eight-row ring keeps its full-span reader. Output visitation, physical padding, byte ownership and event retirement are unchanged. This is invocation-local geometry reuse, not a cross-frame cache or an additional tensor-sized intermediate.

Bounded Compact byte families

The existing small packed entry also serves full-canvas RGB/BGR Identity with Compact INT8 C3 storage. ROI and output extents must match, ROI width is at most 2048 and height at most 4096, source pitch fits the 2D DMA field, and H tiles are complete. Regular representable bands retain their original entries. Other admitted windows own one actual W tile and aligned H pieces in two existing 16KiB source prefixes, with two existing 32KiB output slots. Intermediate H cuts are physically aligned; only the last piece writes the tile's real alignment padding. Odd ROI X, arbitrary W tile widths and real W tails are supported. Unproved H tails, canvas padding or short work keep the original canonical path. Selection occurs before regular-band division or map/sampler setup.

The existing YUV Compact entry also admits bounded full-canvas INT8 C3 Nearest windows for NV12, I420 and NV16 when physical tiles exceed the single-DMA field and at least two full W tiles exist. Independently checked full/tail chunk plans must coalesce at least 32 rows and fit two 16000-byte source slots plus literal three-channel tables in its existing 32KiB source allocation. Two existing 32KiB outputs own exact physical tile prefixes and final alignment padding. Source centers retain the separately rounded FP32 multiply/subtract, floor and clamp; chroma uses absolute source coordinates before subsampling. The cold window helper keeps the separately rounded, volatile FP32 product. Its finite center is bounded$[-0.5,4096)$: signed truncation followed by the integer clamp to $[0,\mathrm{ROI}-1]$ is therefore exactly floor followed by that clamp. Negative first centers still select0, and exact half-integer ties floor rather than round to nearest. This preserves coordinate values and FP32 operation order; it is not a promise of identical incidental floating-point status flags. Only the exact source payload width persists in each private window; grouped output width is a constructor-local product, not redundant retained metadata. Byte samples and fixed-matrix integer color conversion retain the saturated UInt8 boundary, then literal tables perform the same ordered HALF affine/quantization operations. Tables are nonnull; equal rounded coefficients may share a completed table. While each table is generated, every canonical encoded byte for values0…255 is compared with value ^ 0x80. One invocation-local flag permits that byte XOR only when all three channel tables match over their complete domain; aliases inherit their completed table's proof. The color clamp still precedes encoding. A mismatch in any channel retains all three literal lookups. Tables remain fully initialized and available, with no host coefficient guess, null sentinel or changed HALF arithmetic; the flag is rebuilt when the invocation changes. Rejected windows retain the original sparse-row reader. These private family bounds change neither public admission nor numerical tolerances; composed firmware resources and latency require separate target qualification.

Complete neighboring W tiles may share one wider Nearest source rectangle. The planner tries four, then two tiles when at least two complete groups exist and the bounded source/output slots still hold at least32 rows. Leftover full tiles and the final actual-width tile retain independent windows. This family is selected from checked geometry, not a camera/model identifier.

For one tile's compact line $L=3w$, each intermediate chunk uses a multiple of $p=16/\gcd(L,16)$ rows. With group size $g$, the output bound is $gLr\le32768$; alignment is based on each tile, not the grouped width. The final chunk rounds each segment to16 bytes and clears only that tile's alignment padding. Each segment retains its original physical destination; there is no new output layout or frame-sized coordinate map.

The tight source rectangle covers the group's first/last canonical luma samples, including unsampled intermediate rows/columns. Absolute chroma phase, per-plane pitch and plane-start alignment count against the16000-byte slot. For complete multi-tile groups only, local luma/chroma pitches round up to16 bytes when the same conservative source bound still admits the original chunk height. This does not change groups, source samples, chunk counts or numerical expressions. DMA copies each plane's exact payload width into its padded local pitch; local holes are neither read from DDR nor consumed by gathers. Leftover single tiles and the final actual-width tile retain their tight pitches. With $Y$ luma rows, $C$ chroma rows and local pitches $P_Y,P_C$, plane U starts at $A_{16}(Y P_Y)$. NV12/NV16 then require $A_{16}(Y P_Y)+C P_C$ bytes; I420 additionally aligns plane V and requires $A_{16}(A_{16}(Y P_Y)+C P_C)+C P_C$. All plane alignment and row holes count against the unchanged16000-byte source slot. If padded pitches would reduce the admitted row height, the whole grouped family keeps its original pitches. Alignment is a bounded transfer/bank-layout choice, not a measured speed promise.

Wider stripes reduce submitted camera-row fragments but may increase SDK copies/output segments or reread bytes; this is not a latency guarantee. Inactive SIMD lanes clamp to the final pixel of their individual tile. Each tile uses32-lane byte/halfword gathers with two separately rounded FP32 coordinate vectors. Packet-major X/chroma indices remain reused across rows; no packet crosses a physical tile boundary. For either color matrix, every coefficient product and the green-channel sum fit signed16; the greatest absolute bounds are15232 and8704, respectively. Signed16 multiplication and arithmetic right shifts therefore preserve the exact integer color equations. The clamped0…255 RGB codes widen directly into literal HALF-table addresses, without a redundant byte narrowing. Coordinates, color clamp, ordered table quantization, RGB/BGR publication and all rounding boundaries remain unchanged. The last32-lane packet clamps both address vectors before masked stores.

Two source slabs continue input prefetch. Each existing output slot holds at most four separately owned tile segments; every output event retires before slot reuse or worker return. This preserves per-worker16-byte physical write ownership, including actual right/bottom tails. A grouped rectangle that cannot hold32 rows retains the admitted single-tile window or canonical reader.

Bounded next-row input overlap

The ordinary and fixed-Gray workers may issue the next actually visited active output row's input transfers while the current row is sampled. They reuse only the existing eight source-row slots; map and output-window offsets, plane spans, output stores and interpolation operations are unchanged. A pure scalar planner reproduces the original replacement walk. If that walk would evict a current tap, or the following row is not proven to be visited within the owned panel/band, the original synchronous loader remains the fallback. The luma and independent chroma plans must both succeed before committing any future tags or issuing DMA. Every future event is retired before consumption, X-span/batch reuse or kernel return. Box and specialized numerical workers keep their existing loading paths. This removes no required input bytes: it only offers bounded input-DMA overlap, whose latency benefit requires matched device measurements.

The ordinary and fixed-Gray workers may initialize invariant Pad16 ghost bytes once in each invocation's two private output slots. Admission counts only the worker's active-band clear work (or complete owned fallback panels), not an ordinary letterbox's already-repeated padding bands. Live channels, canvas padding and every requested physical output byte are still written each call; no caller-output or previous-job initialization is reused.

Ordinary and Gray fractional Bicubic workers may prepare four exact FP32 X-weight planes in the unused local-arena suffix after both disjoint output slots. The ordinary worker may reserve map space before sizing those slots only when there are no partial or alignment-tail tiles, the original complete full-width band height is unchanged, and every such band still fits the reduced slot. This can reduce local slot capacity, not publication bands or source-row traversal. Insufficient capacity or a changed band height retains the literal sampler. Geometry, polynomial ordering, tap products/additions and final HALF rounding are unchanged. Integral X with fractional Y instead prepares four invariant scalar weights. Cache readiness and bytes are invocation-local; public layout, required padding and source permissions do not change.

Single-tap semiplanar sampling

The ordinary worker also uses its existing aligned UV word reader for Identity and Nearest on NV12/NV16. One initialized two-byte pair supplies the separately widened U and V HALF values; full-source odd ROI phase, clamped inactive lanes, independent chroma row tags and exact source bounds are unchanged. I420 keeps its separate byte-plane gathers. Bilinear and Cubic retain their current sampling order. Color, affine/quantization, canvas padding and physical ghosts still use the same sinks and writers.

The internal NPP_PAIRED_YUV_BILINEAR compile macro covers this paired reader for Identity, Nearest and Bilinear; it is not a new public option.

This removes one duplicate local UV gather/index per 16 sampled pixels, not a DDR pass or any source/output byte, DMA command, event or scratch region. Integer-to-HALF widening remains exact over 0..255. Device latency qualification is separate from numerical/source/code-generation evidence.

INT8 Bilinear family paths

Selection uses format, interpolation, geometry, physical storage and owned work, not a list of image sizes. Ineligible requests retain the canonical sampler. Public tensor, ROI, color, affine and quantization contracts are unchanged.

Packed RGB/BGR Pad16 horizontal-row reuse. Full-canvas Bilinear requests with source ROI width and output width at most 1024, and vertical upsampling or unit scale, can cache two independently rounded horizontal HALF rows. The existing 12 KiB source arena must fit two aligned raw RGB rows and two aligned SoA HALF rows; bounded X maps must also be available. Both current taps are pinned before either cached row is replaced. Batch changes invalidate tags. Each stored row retains the horizontal subtraction, multiplication and addition rounding boundaries; vertical interpolation retains its three HALF boundaries. The result still crosses the canonical saturating UInt8 boundary before the exact affine/quantization lookup. Input lookahead uses disjoint retired raw slots; no additional DDR intermediate or cross-invocation image cache is used.

Shared integral Bilinear used-tap windows. NV12, I420, NV16, RGB/BGR and Gray INT8 image requests can reuse one bounded metadata planner and physical publisher when both ROI-to-destination ratios are positive integers. Packed inputs have a separately compiled owner, so they do not carry chroma reader or color-conversion state. Packed and YUV owners retain distinct private compiled-entry cache slots; these are not public graph IDs and do not change the typed request. Gray may produce Gray or replicated RGB/BGR; YUV and RGB/BGR produce RGB/BGR. Dense, Compact and Pad16 use the same sampler, including horizontal/vertical canvas padding and compressed edge tiles. Odd-center YUV Dense/Pad16 requests retain a separately compiled single-tap owner; its hot stencil carries no even-tap, Gray or Compact branches. The cold checked geometry selects that owner, while the generalized integral owner covers the additional tap/storage families with the same numerical contract. Compiled owners have distinct private cache slots.

For a destination-relative coordinate $d$ and integral ratio $r=S/D$, Bilinear's half-pixel coordinate has the exact first tap and fraction:

$$s(d)=d r+\lfloor(r-1)/2\rfloor,\qquad f=\begin{cases}0&r\text{ odd},\\1/2&r\text{ even}.\end{cases}$$

An odd axis needs one tap; an even axis needs the two adjacent taps. The worker loads only those used tap streams, not every intervening source row. The one-, two- or four-tap UInt8 mean is exact before the canonical saturating RTZ UInt8 boundary: every partial value is dyadic, has magnitude at most 255 and is representable in HALF. This preserves the ordered Bilinear subtract/multiply/add stages rather than approximating them. Existing full-canvas exact-2× owners and their vertical Pad16 letterbox owner keep precedence.

EV admission bounds source and output axes to 4096 and keeps the ROI inside the source. Thus $(d+0.5)r\le S-r/2\le4095.5$ is exactly representable in FP32. The absolute ROI origin is added before dividing chroma coordinates. NV16 has full-height chroma; NV12/I420 use their actual half-height planes, including odd ROI phases. Integer color conversion and the separate HALF affine and quantization stages are unchanged.

Two 16,000-byte source slots plus at most three 256-byte tables fit the 32 KiB source arena. Two 32 KiB output slots hold complete Compact/Pad16 tile groups or aligned Dense row bands. Scaled source pitches must fit the 16-bit DMA fields; valid requests that fail the bounded proof retain the canonical reader. Padding windows transfer no input rows. Empty or tiny worker assignments retain literal arithmetic rather than paying for lookup-table setup.

Odd-center YUV Pad16 may use a separately compiled wider publisher with two 40 KiB output slots. Admission first proves the original center family and the unchanged 16,000-byte per-source-slot capacity, then requires at least one-third fewer X windows: 3 * wider_windows <= 2 * original_windows. The existing paired eight-column renderer may retain one-fifth fewer windows when X is fully active, an internal Y tile boundary separates active rows from canvas padding, and the semiplanar reader stages planes directly (NV16 or NV12 with unit Y ratio). Ragged full-canvas Y alone does not qualify. Other requests keep the one-third rule. The same exact sampler, chroma-plane policy, lookup tables, ghost initialization and event retirement are reused; Dense and all nonbenefiting requests keep the original 32 KiB owner. The wider owner's complete compiled frame, stack and alignment slack must fit the 128 KiB worker budget.

Flattened (batch, Y window) units are assigned cyclically across the actual workers, retaining every X group of an owned Y window together. Local visit ordinal selects ping-pong slots. Each output DMA granule has one owner; physical tile alignment is written once at the complete tile's end, not independently at every short row chunk. Every required RGB, ghost-channel and alignment byte is initialized on each invocation, including retained dirty buffers. All reads and writes drain before storage reuse or return.

Mixed exact/fractional Bilinear. The private mapped INT8 owner also accepts one integral and one fractional axis. The integral axis keeps its exact tap rule; only the fractional axis needs coordinates and HALF fractions. Bounded X maps are invocation-local, retain full-source ROI phase and never cache pixels or coefficient-dependent results across calls. Fully integral axes keep the used-tap or existing exact-average owners.

Mapped YUV Compact interiors and edges. NV12, NV16 and I420 can reuse the fractional mapped Compact owner for output widths at most 672, tile widths that are positive multiples of 16, even tile heights, ROI widths at most 2048 and representable physical tile pitches. At least one axis must be fractional. These bounds account for the rounded final map vector, the separate Y/U/V readers and the complete source/output working set.

Complete full-canvas NV12/NV16 tiles use a separately compiled owner that retains the original two-row-band publisher. Its cold proof removes canvas, partial-lane and planar-format checks from each interior group. Complete full-canvas I420 tiles retain the ordinary mapped owner's two-row-band publisher. Clipped canvases and partial W/H tiles, including I420, use the bounded edge publisher, which gives each worker complete H-tile rows. The mapped 16-pixel interior stays vectorized, only the final fragment is masked, and a compressed tail writes precisely its actual payload and complete-tile alignment residue. Padding-only rows perform no source DMA. This ownership prevents adjacent edge chunks from racing over a shared physical granule. I420 retains independent U/V plane addresses and pitches.

Current luma and chroma taps are pinned independently within the eight-row source arena. Only missing taps of the known next active row are prefetched into disjoint available slots. Sampling can overlap those reads; the next reader waits its owned events before consuming tags. Geometry changes, batch changes and coefficients rebuild or invalidate the appropriate invocation-local state.

Shared exact tables and full-canvas packing. RGB, Gray and YUV INT8 full-canvas owners reuse the same exact finite UInt8-to-INT8 table builder. Only distinct encoded affine coefficient pairs build tables; Gray needs only its live channel. A worker with fewer than 32 owned 16-pixel groups retains the original arithmetic. RGB Pad16 publishes RGB plus the first ghost byte with one word scatter; the required remaining ghosts keep their existing initialization. RGB/Gray source-row pairs use one 2D DMA when the two actual tap rows are adjacent and both source/local pitches fit their hardware fields. Nonadjacent or unrepresentable rows retain the original independent transfers.

The finite UInt8 tables encode the same ordered transform for every input code, not an approximation. With $H$ denoting the canonical HALF rounding boundary:

$$a=H(u-H(o)),\qquad b=H(a\,H(m)),\qquad c=H(b\,H(s)),\qquad q=\operatorname{clip}_{[-128,127]} (\operatorname{rtz\_sat}_{\mathrm{int16}}(c)+z).$$

The production helper remains authoritative for exceptional-value conversion. Combining affine and quantization multipliers is not generally equivalent across these boundaries. Precomposed application coefficients do not change this contract: the kernel applies the supplied affine and quantization multipliers as separate operations.

Exact sampling and bounded packing reuse

These private paths preserve the typed request and ordered sampling, color, affine and quantization stages. Their geometry and tags are invocation-local; changing image, ROI, destination or coefficients always rebuilds the state.

Gray integral Bicubic. For full 16-lane groups with four-to-one ratios on both axes and aligned, unclamped source taps, four word-vector loads replace sixteen byte gathers. With $w=(-3,19,19,-3)$, the sample is:

$$H\!\left(\operatorname{clip}_{[0,255]} \left(\frac{\sum_{j=0}^{3}\sum_{i=0}^{3}w_jw_i p_{j,i}}{1024}\right)\right).$$

The scaled absolute sum is at most $255(3+19+19+3)^2=493680$, so INT32 products and sums are exact. All original FP32 partial sums are dyadic values with this same scale, so the integer stencil preserves the HALF result. Unaligned origins, borders and tails retain the original gathers. For Gray INT8 linear letterbox output, active/mixed and padding-only 4 KiB panels are partitioned separately across workers. Each original physical panel still has one owner; this balances sampling work without changing its order.

Post-sampling UInt8 tables. The integral Bicubic INT8 worker can map the canonical saturating RTZ UInt8 result through a 256-entry table per distinct coefficient pair. Entries use the same separately rounded HALF subtraction, affine multiplication, quantization multiplication and final integer clipping. Equal immutable coefficient encodings share one table. Tables borrow only a proved untouched prefix or suffix of source slot 7, with a 64-byte fringe gap and space for all three tables. The proof includes whole-row reads and packing, not only the currently narrowed edge span. Insufficient space or short work retains literal arithmetic; source pixels and output slots never alias a table.

Quarter-phase Bicubic weights. In the ordinary worker, ratios satisfying $2S_x/D_x\in\{9,11,13,\ldots\}$, with admitted axes at most 4096, produce exact quarter phases. A 64-byte immutable suffix bank stores the eight ordered FP32 weights for phases 1/4 and 3/4. Canonical coordinate, floor, ROI origin, clamping, tap order and accumulation remain unchanged. Other nonintegral ratios use a bounded full X-weight map when profitable or the literal polynomial.

Shared Bicubic YUV stencil. The ordinary worker selects the planar I420 or paired NV12/NV16 body once per stencil. NV12/NV16 extract both UInt8 components from the initialized UV pair and convert unsigned integer lanes directly to FP32: every integer in [0,255] is exactly representable in both HALF and FP32. I420 retains its separate U/V-plane reads. All supported output dtypes and layouts retain row-major tap order, separately rounded wx*wy and pixel*weight products, ordered FP32 additions, clamping and final HALF conversion before the unchanged color/output stages. Absolute odd ROI chroma phase, inactive-lane source bounds, DMA retirement and physical padding ownership are unchanged.

Packed RGB/BGR and BoxAverage. A sampled cubic ROI whose four-tap X windows do not overlap can expand only those windows from three-byte pixels to private four-byte words. Windows are visited in descending source-X order, and all three raw-byte vectors are loaded before word stores, so expansion cannot overwrite unread lower pixels. Other ROIs retain full-span packing. Compressed physical edges reuse their completed tile-local X maps rather than repeating polynomial preparation. Wide Bilinear RGB rows can place bounded X indices and HALF fractions in unused row tails when full raw-row and SIMD-tail capacities prove non-overlap; otherwise the literal sampler remains. RGB/BGR BoxAverage can load a proven unclamped four-pixel, twelve-byte cell with halfword gathers, retaining the same integer sum, count, division and HALF conversion in Dense, Compact and Pad16. Dense output additionally combines two adjacent interior groups into the existing 32-pixel publisher; tiled storage retains its bounded canonical writer. Unproved source cells use the original byte gathers. The tiled four-column RGB/BGR family owns a separately compiled shared-body entry, selected once from checked storage, format and exact horizontal ratio. Dense and unrelated samplers retain their original generic compilation context. The split changes neither admitted dtypes nor the sampler's ordered reductions, color/affine conversion, physical ghosts or boundary fallback.

Nearest whole bands and useful lanes. Bounded two/four/eight-row bands may stage selected luma/chroma rows with constant-pitch 2D DMA. A band must divide the physical tile height, fit the existing output slot and own complete output DMA granules. Pad16 workers choose one common partition from the minimum owned clear work; worker-local decisions must not change that partition. Odd Compact C3 INT8 H tiles retain the original per-row reader and lookahead. Compact YUV Nearest can reuse an exact X map and repeated selected-Y colors within an invocation; duplicate-row reuse requires the full source-row identity. The POINT Pad16 W8 worker pairs adjacent tiles to use sixteen live SIMD lanes, retaining separate exact-width edge and padding writers. Every input and output event retires before storage reuse or return.

RGB/BGR Identity and Nearest INT8 byte-domain sampling

Ordinary RGB/BGR-to-RGB/BGR INT8 requests that have no earlier dedicated route use a private Identity/Nearest owner. An interior raw UInt8 sample is already in the post-sampling table's exact input domain, so an admitted channel table maps it directly to the final INT8 code without storing/reloading a HALF pixel. The table still evaluates every ordered HALF affine/quantization stage; this shortcut does not combine coefficients. Short work without tables, canvas padding and fragment groups retain the original conversion path. Gray Identity/Nearest requests retain their existing workers. Geometry, tables and row contents are rebuilt for each invocation; the canonical output writer still initializes every required physical byte and drains all DMA before return.

Compact packed-image internal bands

Full-canvas packed RGB/BGR Bilinear windows split tall, complete Compact tiles into internal H bands of at most 256 rows before fitting the existing 16 KiB source and 32 KiB output windows. Adjacent W-tile bands share a bounded source rectangle and horizontal HALF cache; the caller's tile dimensions do not change. A multi-W sub-band publishes a 2D rectangle whose destination pitch is the full physical H-tile extent, not the shorter local band. Its pitch must fit 65,535 bytes. Taller/wider tiles that fail that proof retain single-W publication; ragged physical tiles retain the existing complete-tile window path.

The final short internal band uses its actual height. Each copy writes only its owned tile-band bytes, never the intervening H rows, and every input/output event retires before slot reuse and return. This changes traversal and transfer geometry only; the channel writer and all numerical rounding remain unchanged.

Memory-bandwidth lower bound

Using 16 GB/s ($16\times10^9$ bytes/s) as an aggregate read/write planning ceiling, the ideal transfer lower bound in microseconds is:

$$t_{\min}=10^6\frac{B_{\text{mandatory input transfers}}+ B_{\text{physical output writes}}}{16\times10^9}.$$

Count actual input spans, not untouched allocation capacity. Count physical output padding and ghosts, not only logical channels. A dense 640×640 C3 INT8 output writes 1,228,800 bytes: its output-only floor is 76.8 µs. Compact tiles match that size only when no extra tile-end alignment bytes are needed. Pad16 requires 6,553,600 bytes: its output-only floor is 409.6 µs. Neither includes computation, rereads, descriptor work or submission/completion. This ceiling is a planning bound, not measured sustained bandwidth or a latency guarantee.

Sampling implementations

These optimizations preserve the sampling contract. They change traversal, staging or equivalent arithmetic—not the public modes.

Row-invariant sampling state

The ordinary and Gray workers prepare Bilinear's rounded HALF Y fraction and fractional Bicubic's four FP32 Y weights once per sampled output row. The loader recomputes that private scalar state whenever it stages a sampled row, while issued input DMA progresses; geometry is rebuilt for each invocation. Pixel groups reuse the same rounded bits; X weights, tap accumulation order and final HALF conversion are unchanged. Already-prepared RGB cubic maps retain their own row weights; integer, packed, dedicated semiplanar and virtual-ROI workers keep their existing sampling paths. No image data or state is retained across invocations.

BoxAverage accumulation and byte conversion

The ordinary worker traverses each Box footprint once for all output channels, sharing its loop bounds and active-lane mask. RGB/BGR retains the named channel permutation, Gray is sampled once, and YUV retains independent chroma row tags and full-source chroma phase. Sampling still precedes color conversion and ordered affine/output conversion. Identity, Nearest, Bilinear and Bicubic keep their separate sampling paths; a scalar interpolation value selects the sampler before the SIMD tap loop.

The implementation accumulates the bounded UInt8 tap sum exactly in INT32, multiplies by an explicitly encoded FP32 reciprocal for the tap count, then rounds to FP16. This is not the target's approximate reciprocal instruction. For this bounded domain, the Clang/OpenCL host-model test configuration exhaustively checks all 530,464 possible sums/counts against the specified FP32-division then FP16-rounding reference. For a fixed output row, at most two horizontal tap counts occur, so the SIMD path selects between two broadcast constants rather than doing per-lane table lookups. This equivalence does not authorize integer floor division before the half-rounding boundary, arbitrary reciprocal approximations, or changes to BoxAverage's touched-cell definition.

A private linear INT8 RGB/BGR BoxAverage owner handles exactly four horizontal cells when the destination is at least 64 pixels wide and has enough work for the existing channel tables. Its interiors process 32 complete pixels per SHORT32 group; other samplers do not contain this per-group branch. Admission already bounds vertical taps to eight, so each channel sum is at most 4 * 8 * 255 = 8160. Aligned local halfword gathers preserve the named channel order; strict interior bounds keep all widened reads inside initialized ROI bytes, including an odd ROI origin. The original FP32 reciprocal, HALF nearest-even result, UInt8 truncation and exact channel table remain the conversion sequence. Borders, partial groups, tiled output and other cell widths use the existing 16-pixel sampler.

Shared YUV taps and exact sampling

The ordinary fractional YUV path shares this sixteen-tap traversal and its clamped full-source X coordinate across Y, U and V. Each channel keeps a separate, ordered FP32 accumulator, the same final clamp and FP16 rounding. NV12/NV16 fetch both bytes of an aligned worker-local UV pair together; I420 continues to gather from its separate U and V plane regions. The independent chroma row tags, including repeated edge rows and odd ROI origins, are unchanged. This local alignment does not require aligned DDR plane addresses: staged row slots and even source width establish it. Every clamped pair is wholly inside the initialized source-row extent, including the last chroma pixel. Gray, packed RGB/BGR and integral Bicubic retain their existing sampling paths.

For ordinary three-channel INT8 YUV Bicubic with no earlier specialization, a private owner is selected when output width is at most 2048 and the ROI height is at least the destination height. Four consecutive/clamped luma X taps need at most three distinct chroma pairs; the second pair is selected lane-wise from the first or third. An identical initialized NV12 chroma-row offset can reuse those raw pairs. NV16 rows are distinct unless the ROI border itself repeats; I420 retains separate U/V gathers. The sixteen weight_x * weight_y products and each channel's row-major FP32 additions stay ordered: sample reuse does not combine weights, reassociate sums or introduce FMA. Vertical upsampling keeps the original worker, as do other dtypes and earlier dedicated routes.

Exact sampling specializations

The implementation computes sampling geometry once per SIMD pixel group and shares it between input channels. Gray input is sampled once; Gray-to-RGB still applies three independent output affine transformations.

For general bilinear sampling, the loader already supplies first = floor(sy). The vertical fraction reuses sy - float(first), then rounds to FP16. Admitted coordinates are finite and bounded, so first is exactly representable in FP32. The ordinary row loader shares a bounded scalar floor helper. For validated positive sampling coordinates, it extracts the FP32 integer significand instead of converting a fractional value early. The original separately rounded coordinate expression and subsequent sampling operations remain unchanged. Raw-bit admission accepts signed zero and positive values from 2^-25 up to (but excluding) 4096; negative or outside-domain values retain the literal SDK floor and integer conversion. Other workers retain their original floor code. The helper neither reads nor writes floating-point control/status registers.

Clearing the fraction's half sign bit preserves the canonical positive zero, including sy = -0; all other valid fractions are nonnegative. Integer-bit broadcasts preserve those half bits without additional rounding. The horizontal and vertical lerps retain their separate half subtraction, multiplication and addition boundaries; this reuse does not introduce FMA or reassociation.

When an effective ROI extent is an integer multiple of the destination extent, the half-pixel coordinate has an exact phase: zero for an odd ratio and one half for an even ratio. Integer index arithmetic replaces repeated coordinate work for that axis, without changing the source-border clamp or absolute chroma phase. A zero-phase bilinear axis does not gather an unused neighboring tap. For an odd integer vertical ratio, staging also omits the unused second row. The integer-ratio bicubic path similarly stages only its center row when the vertical ratio is odd; this staging reduction requires both axes to satisfy that exact bicubic specialization. When both axes have integer ratios, bilinear sampling uses exact INT32 sums scaled by one, one half or one quarter before FP16 conversion. Fractional quarters are retained until the normal color/output stage; they are not prematurely truncated to bytes.

Bicubic uses a restricted exact integer path only when both axes have integer ratios. Its axis weights are [0,1,0,0] at zero phase or [-3,19,19,-3]/32 at half phase. The signed INT32 weighted sum and power-of-two scaling preserve the canonical FP32 result over UInt8 inputs; clamping and FP16 rounding still follow. Other ratios retain the ordered FP32 polynomial and tap accumulation. These are private eligibility rules, not new public interpolation modes or permission for general reassociation/FMA.

ROI-list execution

One Runtime submission carries the list. The EV control processor launches its accepted crops in order; numerical list iteration is not an A65/plugin loop. In-frame crops reuse the existing specialized workers. Out-of-frame crops use a separately compiled virtual-row loader sharing the same numerical code; ordinary workers contain no virtual-row branch. A bounded SIMD/DMA zero worker clears unused physical output slots.